High Energy Efficiency Spatial Parallel Stochastic Computing for Precision Scalable Neural Processing Unit

A precision-scalable neural processing unit, considering the quantization-sensitive of each neural network layer, has large hardware redundancy in multiplication units and shift logics. In this paper, we explore a spatial parallel stochastic computing (SPSC) precision-scalable architecture to reduce hardware redundancy. The conventional SPSC multiplier has large accuracy loss, so we analyze the error component and propose an error compensation SC (ECSC) multiplier. To reduce the hardware cost, the bitbrick (BB) in fusion-based precision-scalable architecture is replaced by stochastic bitbrick (STOBB), which is composed of a fine-grained ECSC multiplier. The proposed SC architecture supports 2/4/8-bit operation. Our design is synthesized under SMIC 55nm CMOS technology. Experiments show that our design achieves a 2.048 TOPS/W energy efficiency as well as 2.21× area efficiency in comparison to the state-of-the-art designs.