A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error

The quadrature phase clocks are important elements in digital programmable transceivers in communication system applications. However, current solutions in quadrature clock generators for broad frequency ranges need more phase accuracy, and they suffer from substandard phase noise performance and excessive power consumption. To address these challenges, this paper proposes an inverter-based quadrature-phase clock (I-QPC) generator. The I-QPC generator utilizes inverters as delay elements to achieve the desired phase without using poly-phase type-1 filters because inverters are simpler to design and optimize for different phase delays. The system implements a phase-averaging mechanism using the delayed and interpolated signals, leading to quadrature-phase signals. The proposed technique has been validated in 28nm standard CMOS technology after post-layout parasitic extraction. The I-QPC generator operates over the broad frequency range (1GHz to 6GHz) and occupies an active area of 0.0005mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The post-layout simulation results show that the phase error is ±0.29<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> while operating at 6GHz. The phase noise is -131.7dBc/Hz at an offset of 1MHz with a power consumption of 2.9mW. The I-QPC generator’s figure of merit (FoM) is 217.3dBc/Hz at 1MHz offset frequency, which is better than state-of-the-art architectures. The performance of the I-QPC generator was further evaluated in hardware by implementing the circuit on a breadboard using the SN74HC04N inverter IC, and it demonstrated the successful generation of the quadrature signals at 1MHz frequency.