Design and Analysis of Latch-Type Comparators for Cryogenic Operations

A low-power, high-speed latched comparator is the most crucial component in high-speed analog-to-digital converters (ADCs). With recent advances in quantum sensing and quantum computing, these ADCs need to operate at cryogenic temperatures. However, the performance of existing latched-comparators at cryogenic temperatures has not been thoroughly evaluated. In this paper, we address this gap by characterizing and comparing five representative comparator architectures. We elucidate their operational principles at both cryogenic (4K) and room (300K) temperatures, utilizing TSMC 28nm CMOS technology. Our study showed that, the triple latch design achieves the best performance at cryogenic temperature, while at room temperature, the modified strong-regeneration design has the best performance.