RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs

General-Purpose GPUs (GPGPUs) are ideal for parallel processing and high throughput. However, efficient on-chip memory use is challenging due to resource conflicts between threads. This leads to sub-optimal throughput, highlighting the need for better memory designs. As compute demand grows, GPUs with more Streaming Multiprocessors (SMs) emerge, increasing bandwidth needs and intensifying Network-on-Chip (NoC) traffic. Current GPUs partition the shared Last-Level Cache (LLC) into uniform slices shared by all SMs. While this reduces miss rates, workloads with high inter-SM data sharing benefit more from private LLCs, which reduce contention and improve bandwidth. We propose a dynamic profiling method to evaluate data sharing across SMs during execution. Using this, we present a logistic regression-based decision mechanism to switch between shared and private LLC configurations at runtime, with a twenty five thousand cycle reconfiguration epoch (compared to 1 million cycles in the state-of-the-art). Our approach boosts performance by up to 56% over the baseline and 29% over state-of-the-art methods. It also reduces stalls by 71% over the baseline and 59% over state-of-the-art approach.