Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs

This paper presents an in-memory computing architecture of a convolutional layer useful to build binary deep neural networks aimed to work on pixel streams coming from an image sensor at a rate of one image row per clock cycle. The architecture corresponds to a hidden layer of a network and is capable of performing binary convolutions by combining a set of interlaced columns of conventional 6T SRAM cells with 10T in-memory computing cells. This arrangement leads to a weight–stationary architecture, where input activation values are sequentially stored in the 6T SRAM columns while the 10T cells store the weights and perform the convolution operation. The proposed pipelined operation, allows that the requirements of silicon area to store and process the image are reduced by a factor equal to the image height compared to a conventional in-memory architecture. The circuit has been synthesized on a 180 nm standard CMOS technology. Simulation results show that the circuit is able to perform process image inferences at a rate of 5M S/s, at a expense of 194,1 fJ/operation, achieving an overall efficiency of 5.15 TOPS/W.