An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers

This paper presents an ultra-low power 915 MHz Local Oscillator (LO) with adaptive frequency calibration algorithm for IoT Wake-Up Receivers (WURs). The proposed algorithm can adaptively adjust and minimize the calibration time of each bit oscillator tuning word (OTW) as well as the number of OTWs that require re-calibration after open-loop time. These two features help reducing the average LO power consumption by minimizing the closed-loop frequency calibration time. The duty cycle of the closed-loop time can also be adjusted flexibly to further reduce the average LO power consumption at a given frequency stability requirement. Fabricated in 40-nm CMOS, this proposed algorithm reduces the frequency calibration time from 108 μs to 42 μs, achieving a time reduction of 61%. An average LO power consumption of 93 μW at a 5% closed-loop time duty cycle is measured with a frequency accuracy of 120 ppm.

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Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043340
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers

Hao Min, Ronghua Ni, Meng Liu, Tian Huang et al.
1 links
Radio Frequency Integrated Circuit Design
article

An Ultra-Low Power 915 MHz LO with Adaptive Frequency Calibration for IoT Wake-Up Receivers

Hao Min, Ronghua Ni, Meng Liu, Tian Huang, Qianhui Li, Xiaohua Yu, Xianhong Xiu
article en

Abstract

This paper presents an ultra-low power 915 MHz Local Oscillator (LO) with adaptive frequency calibration algorithm for IoT Wake-Up Receivers (WURs). The proposed algorithm can adaptively adjust and minimize the calibration time of each bit oscillator tuning word (OTW) as well as the number of OTWs that require re-calibration after open-loop time. These two features help reducing the average LO power consumption by minimizing the closed-loop frequency calibration time. The duty cycle of the closed-loop time can also be adjusted flexibly to further reduce the average LO power consumption at a given frequency stability requirement. Fabricated in 40-nm CMOS, this proposed algorithm reduces the frequency calibration time from 108 μs to 42 μs, achieving a time reduction of 61%. An average LO power consumption of 93 μW at a 5% closed-loop time duty cycle is measured with a frequency accuracy of 120 ppm.

Fudan University (CN), State Key Laboratory of ASIC and System
Affordable and clean energy
Openalex Percentile: Top 87%
Radio Frequency Integrated Circuit Design
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