iSPAZ: An Improved Switched-Capacitor Ping-Pong Voltage Generator with Auto-Zero for Ultra-Low-Power Internet of Everything Systems

This paper presents a Threshold Voltage Generator (TVG) for IoE receivers featuring ULP comparators (CMPs). Prior art TVGs dynamically generate the CMP threshold to enable the receiver to process time-varying received power. However, they require a large area and additional circuits to ensure that the IoE system operates with minimal energy consumption regardless of temperature changes. The proposed TVG has been implemented in a 90-nm STMicroelectronics CMOS technology with a 0.6-V supply, targeting 1-kbps datarate. It occupies 40x less area than RC-based TVGs, consumes 2.2 nA and ensures a 3.5-dB SNR boost without affecting IoE system performances. When compared to previous art, it allows for a 10x energy consumption reduction without requiring any additional circuits. Monte Carlo simulations of an ULP receiver equipped with the proposed TVG show a 0-% Packet Error Rate from -40 °C to +85 °C.

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Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043300
Primary Topic
Low-power high-performance VLSI design
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article
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article

iSPAZ: An Improved Switched-Capacitor Ping-Pong Voltage Generator with Auto-Zero for Ultra-Low-Power Internet of Everything Systems

M D'Addato, Alessia Maria Elgani, A. Gnudi, Eleonora Franchi Scarselli
Low-power high-performance VLSI design
article

iSPAZ: An Improved Switched-Capacitor Ping-Pong Voltage Generator with Auto-Zero for Ultra-Low-Power Internet of Everything Systems

M D'Addato, Alessia Maria Elgani, A. Gnudi, Eleonora Franchi Scarselli
article en

Abstract

This paper presents a Threshold Voltage Generator (TVG) for IoE receivers featuring ULP comparators (CMPs). Prior art TVGs dynamically generate the CMP threshold to enable the receiver to process time-varying received power. However, they require a large area and additional circuits to ensure that the IoE system operates with minimal energy consumption regardless of temperature changes. The proposed TVG has been implemented in a 90-nm STMicroelectronics CMOS technology with a 0.6-V supply, targeting 1-kbps datarate. It occupies 40x less area than RC-based TVGs, consumes 2.2 nA and ensures a 3.5-dB SNR boost without affecting IoE system performances. When compared to previous art, it allows for a 10x energy consumption reduction without requiring any additional circuits. Monte Carlo simulations of an ULP receiver equipped with the proposed TVG show a 0-% Packet Error Rate from -40 °C to +85 °C.

STMicroelectronics (Italy) (IT), University of Bologna (IT)
Affordable and clean energy
Openalex Percentile: Top 87%
Low-power high-performance VLSI design
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