A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm

This paper proposes a novel digital voltage regulator architecture for System-on-Chip (SoC) applications. The architecture includes an Analog Nested Loop, which improves the regulator's performance. Implemented in 28nm technology, the regulator occupies an area of 0.011mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a total capacitance of 10.6pF. Measurement results show a Power Supply Rejection Ratio (PSRR) of -44dB at 1MHz and a voltage ripple of 3.61mVpp when the Analog Nested Loop is enabled. The regulator is also tested with a Phase-Locked Loop (PLL) oscillator, and the resulting PLL Phase Noise and Jitter are compared to those obtained with an external, clean supply source. Specifically, the Phase Noise at 100kHz improves from - 96dBc/Hz to -97.5dBc/Hz, and the absolute Jitter improves from 97psrms to 95psrms, when the Analog Nested Loop is enabled.