HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules

As the beginning stage of physical design, floor-planning is critical to the quality of chip design. However, with the widespread use of hierarchical modular design and reusable modules, floorplanning for large-scale systems-on-chip (SoC) has become more complex. Reusable modules must be efficiently identified and utilized to address this complexity while considering their symmetry. In this work, we propose HieRFP, a framework for identifying reusable modules and performing floorplanning considering symmetry. Firstly, a hierarchical clustering method is proposed to automatically recognize the symmetry of reusable modules based on netlist and module outlines. Then, the hierarchical representation combined with the corner stitching compliant-based method is used to enable floorplanning that considers symmetry and overcomes the challenge of rectilinear modules. Experimental results demonstrate the superiority of HieRFP, achieving better optimization in terms of wirelength and area compared to existing floorplanners, effectively exploiting the symmetry of reusable modules.