A Piecewise Multi-Correlation Based Digital Background Calibration Scheme for Pipelined ADCs

This paper proposes a digital background calibration scheme for the compensation of the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. The proposed calibration method, called the piecewise multi-correlation estimation (PMCE) technique, injects two pseudo-random number (PN) sequences within two adjacent dither windows to extract gain coefficients. This method transforms the estimation of nonlinear gains into the estimation of two linear gains, thus achieving rapid convergence. The proposed calibration scheme does not result in the output swing degradation of the multiplying DAC (MDAC) due to dither injection. The required modification to analog circuits involves only three additional comparators and a capacitor for dither injection. Monte Carlo simulation results of a 14-bit 1.3GS/s pipelined ADC show that the average SFDR of the ADC is improved from 59.61 dB to 91.11 dB.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043256
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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A Piecewise Multi-Correlation Based Digital Background Calibration Scheme for Pipelined ADCs

He Tang, Zhifei Lu, Lingfeng Bian, Xizhu Peng et al.
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Analog and Mixed-Signal Circuit Design
article

A Piecewise Multi-Correlation Based Digital Background Calibration Scheme for Pipelined ADCs

He Tang, Zhifei Lu, Lingfeng Bian, Xizhu Peng, Wei Zhang, Yutao Peng
article en

Abstract

This paper proposes a digital background calibration scheme for the compensation of the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. The proposed calibration method, called the piecewise multi-correlation estimation (PMCE) technique, injects two pseudo-random number (PN) sequences within two adjacent dither windows to extract gain coefficients. This method transforms the estimation of nonlinear gains into the estimation of two linear gains, thus achieving rapid convergence. The proposed calibration scheme does not result in the output swing degradation of the multiplying DAC (MDAC) due to dither injection. The required modification to analog circuits involves only three additional comparators and a capacitor for dither injection. Monte Carlo simulation results of a 14-bit 1.3GS/s pipelined ADC show that the average SFDR of the ADC is improved from 59.61 dB to 91.11 dB.

University of Electronic Science and Technology of China (CN)
Openalex Percentile: Top 86%
Analog and Mixed-Signal Circuit Design
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