A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse

Sparse deep learning has significantly reduced computational costs; however, its irregular distribution of non-zero data complicates data flow, limits data reuse, and increases on-chip SRAM access, thereby elevating chip power consumption. To address these challenges, this work maximizes data reuse to minimize SRAM access through two approaches. First, we propose Effective Index Matching (EIM), which efficiently searches and arranges non-zero operations from compressed data. Second, we propose Shared Index Data Reuse (SIDR), which coordinates operations across Processing Elements (PEs) to regularize their SRAM data access, thereby enabling all data to be reused efficiently. Our approach reduces the access of the SRAM buffer by 86% when compared to the previous design, SparTen. As a result, our design achieves a 2.5× improvement in power efficiency compared to state-of-the-art methods while maintaining a simpler dataflow.