A 49.7-fs, 10.29-to-12.75 GHz Fractional-N ADPLL with a New Quad-Core Class-F₃ Oscillator

This paper presents a fractional-N all digital phase locked loop (ADPLL) based on a new quad-core class-F<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> oscillator, which reduces the out-of-band phase noise of ADPLL. The LC tank of the proposed oscillator incorporates both parallel and series resonant cavities compactly. It increases an additional impedance peak around the third-harmonic of the fundamental oscillation voltage, thus enforcing a pseudo-square voltage waveform around the LC tank. Consequently, the effective impulse sensitivity function (ISF) decreases, thereby reducing the phase noise. Furthermore, the proposed topology demonstrates low phase noise penalty during multi-core resonance. The ADPLL is implemented in a 40nm CMOS process. The simulated phase noise of the quad-core class-F<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> oscillator at 1MHz offset varies from -124.5 to -126.1dBc/Hz depending on the output frequency, which ranges from 10.29 to 12.75GHz. The oscillator consumes 24.36mW from the supply and exhibits a figure-of-merit (FoM) of 192.5dBc/Hz. Ultimately, the ADPLL utilizing the proposed oscillator exhibits an excellent RMS jitter of 49.7fs and achieves a FoM of -250.5dB.