Topology-Guided Optimization Methodology for High-Efficiency Power Amplifier Design

Power amplifiers play a critical role in wireless communication systems, where achieving desired performance metrics such as linearity, gain, and efficiency often requires careful design trade-offs. Traditional design approaches heavily rely on load-pull techniques and designer experience for output matching network topology selection, resulting in lengthy design cycles and potentially suboptimal solutions. This paper presents an automated topology exploration methodology that eliminates the need for load-pull procedures by directly optimizing the matching network topology based on performance metrics through simulated annealing and linear optimization. The effectiveness of the proposed approach is demonstrated through a 3.5 GHz power amplifier, implemented with a single CG2H40010F GaN HEMT, which achieves a power-added efficiency (PAE) of 55% and a third-order intermodulation distortion (IMD3) of -30 dBc within a 20 MHz bandwidth at an output power of 37 dBm in board-level electromagnetic (EM) simulations, while significantly reducing the design cycle to under 3 hours. The proposed design was fabricated and experimentally characterized to validate its performance.