A 67.51 dB SNDR 137.8 µW SAR-Assisted Slope ADC with High-Linearity Analog Slope and Low Switching Energy

This paper presents an energy-efficient hybrid analog-to-digital converter (ADC) that combines a 5-bit successive approximation register (SAR) ADC for coarse conversion and a 6.5-bit analog-slope ADC for fine conversion. Benefiting from input range scaling by coarse SAR ADC, the linearity of the analog-slope ADC is significantly improved. The switching energy to drive the digital-to-analog converter (DAC) is minimized because the analog-slope ADC reuses the capacitor array of SAR ADC without additional capacitors to generate ramp. The ADC is implemented in 180 nm CMOS technology. At a sampling rate of 1 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 67.51 dB and a spurious-free dynamic range (SFDR) of 74.13 dB, particularly when the input approaches the Nyquist frequency, while consuming 137.8 µW from a 1.8 V supply. The resulting Walden and Schreier figures of merit are 72.30 fJ/conversion-step and 163.03 dB, respectively.