A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator

This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power consumption, transistor size, and offset, a reconfigurable reference-embedded comparator is proposed. The comparator is first configured with 7 embedded reference voltages, which can complete the conversion of 3 bits in one cycle. The 3-bit/cycle comparator is then reconfigured to 1-bit/cycle in the last conversion cycle, with improved noise performance and reduced the offset mismatches between the seven latches. As a result, the ADC achieves relatively good precision with considerable power efficiency. A design example of 1-GS/s 7-bit SAR ADC in 40nm CMOS technology is presented. Simulation results show that the ADC achieves a spurious free-dynamic-range (SFDR) of 53.98 dB a signal-to-noise-and distortion ratio (SNDR) of 42.51 dB, with a figure-of-merit of 27.3 fJ/conv.-step.