Analysis of Sub-Sampling PLL False Lock and Lock-in Range Estimation

The Sub-sampling PLL (SSPLL) has attracted significant interest from researchers due to its low phase error and high operating frequency. However, the sub-sampling phase detector (SSPD) is sensitive only to phase error, not frequency error, which may cause false locking into undesired frequencies. This paper provides a detailed analysis of the sub-sampling process and discusses false locking scenarios. Furthermore, the lock-in range, which is the boundary between the system's linear and non-linear behavior, is also investigated. It is a key characteristic of system stability and a constraint in the design of auxiliary devices. This paper develops a state-space model that considers the sinusoidal characteristics of the SSPD to analyze frequency acquisition behavior and estimate the lock-in range.