A 6.86mW 1.5 GS/s 9 b Pipelined SAR ADC with TDC-Assisted Residue Quantization

This paper proposes a 1.5 GS/s 9-bit two-stage pipelined SAR analog-to-digital converter (ADC) in 28 nm CMOS. Simultaneously with amplification, the inter-stage residue is converted to time-domain (TD) and quantized by a TDC. This results in significant resolution improvement of the second stage under the speed of 1.5 GS/s. A double-edge quantized TDC with improved time resolution is proposed for higher conversion speed in the time domain and less power consumption. Moreover, a cascode switching inverter-based open-loop amplifier is proposed featuring low gain error, fast settling, and low power. With a sampling speed of 1.5 GS/s, the simulation results show that the ADC achieves 55 dB SNDR and 66.7 dB SFDR at the Nyquist frequency and 1-V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf> input swing, while the power consumption is 6.86 mW, yielding a Walden FoM of 10.2 fJ/con-step.