A Two-Phase, Single-Comparator, Comparison-Reference-Free Level Crossing ADC for Time-Sparse Applications

A novel discrete-time, level-crossing analog-to-digital converter (LC-ADC) is proposed in this paper. The proposed LC-ADC exploits only one comparator for fully-differential implementation. By using a single comparator twice for each sample instead of using two separate comparators, significant area saving is achieved. The proposed DT LC-ADC is implemented using 180-nm standard CMOS technology with 8 bits of resolution, targeting a 10-kHz bandwidth. Post-layout simulation results indicate that the ADC consumes 18.94μW for a 10-kHz input signal at a supply voltage of 1.2 V. The LC-ADC achieves 11.16-bit ENOB, 68.96 dB SNDR, and 79.95 dB SFDR within the signal bandwidth, and 8.22-bit ENOB, 51.29 dB SNDR, and 55.73 dB SFDR over the full bandwidth.