SRAM-Based Ring Oscillators as Nonlinear Compute-in-Memory for Low-Power Communication

This paper presents two designs of digitally controlled ring oscillators (DCRO) using SRAM-inspired cells in a commercially available 22 nm technology node. The proposed design offers a compact, compilable, DCRO capable of rapid transition between digitally selectable frequencies. Two designs are conducted on a commercially available 22 nm technology node, a compact minimal footprint design occupying 25.58μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area (Design-I) and a scaled up design occupying 50.5μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (Design-II). Extensive simulations validate low transit time between frequency-states (≤15ns on post-extracted netlists), while offering a tuning range of 700 MHz and 1.736 GHz for Design-I and Design-II respectively. Design-I performs competitively with state-of-the-art ring oscillators, consuming 42.5 μW from a 0.8 V supply while achieving a figure of merit (FoM) of 144.79 dBc/Hz for a 1.05 GHz frequency, While Design-II, consuming − 83.8 μW from a 0.8 V supply demonstrates an of –174.01 dBc/Hz for a 1.92 GHz local oscillator signal. This outperforms existing freerunning oscillators, delivering results competitive with those achieved using a PLL.