Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals

This paper presents a novel Dynamic-Window (DW) Digital-to-Analog Converter (DAC) switching technique to enhance the power efficiency of the Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). DW is achieved by dynamically adjusting the reference voltage used by the DAC when the input signal amplitude falls within a certain pre-specified window. The proposed DW is implemented by choosing combinations of DAC slices to effectively create an attenuation of the reference voltage thus dynamically adjusting the SAR ADC’s successive approximation window. This method monitors the input signal amplitude using a coarse front-end (FE) circuit that can be easily implemented with negligibly small energy overhead. DW is particularly energy-efficient for real-world signals with a high Peak-to-Average Ratio (PAR) such as audio and OFDM signals in wireless communication. The effects of DW on a 12-bit 1MS/s SAR ADC are simulated in MATLAB<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> for a Gaussian distributed input signal with a 6σ, 8σ input full-scale (FS) range, demonstrating its ability to reduce DAC energy consumption respectively by 35%, 41% with 2-level DW and 45%, 54% with 4-level DW. The simulations also explore the effects of DW in the ADC performance metrics such as Signal-to-Noise and Distortion Ratio (SNDR), Differential Non-Linearity (DNL), and Integral Non-Linearity (INL) to show DW can be implemented without major degradation in ADC performance for DAC capacitor mismatch as high as 2.5% per fF.