A High-Performance In-Memory Multi-Bit Adder Based on TST-MRAM

In traditional von-Neumann architecture, the memory and the arithmetic logic unit (ALU) are separated. The extra overhead caused by data transfer limits the performance of ALUs in data-intensive scenarios. Compute-in-memory (CiM) architecture based on emerging non-volatile memories (NVMs) has been proven to be effective in addressing the "memory wall" issue. However, current NV-CiM schemes primarily focus on the Boolean logic paradigm, limiting the parallelism of multi-bit computations. In this paper, we propose a high-performance in-memory multi-bit adder based on the toggle spin torque MRAM crossbar array. We use the time-based sensing amplifier to implement majority logic in the crossbar array. Based on majority logic gate, we design a multi-bit parallel-prefix adder. Compared to the multi-bit adders implemented based on Boolean logic gate, our work reduces the number of memory read/write operations and improves the computational parallelism. Moreover, the proposed multi-bit addition scheme exhibits O(log<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>(n)) latency and requires 6n cells for n-bit adder.