A 4kb 4T eDRAM with Balanced Retention Time Adjustment

Gain-cell (GC) based eDRAM has been a promising memory topology due to the lower area footprint and energy consumption than its SRAM counterpart. However, the eDRAM suffers from a short retention time in finer technology nodes. Enhancing the retention time requires both pMOS and nMOS devices, but this inadvertently increases the cell size due to the minimum spacing between them. Further, the retention time is dominated by either logic ‘1’ or ‘0’, lowering the overall retention time. In our work, we propose an nMOS-only GC-based 4T GC-eDRAM memory topology that occupies an area comparable to the 3T GC-eDRAM and enhances the retention time by balancing logic ‘0’ and ‘1’ via controlling the leakage path. Designed in GlobalFoundries 22-nm FD-SOI, the post-layout simulation of a dual port 128×128 (4kb) eDRAM memory array shows 610 μW and 490 μW of write and read power consumption at 250 MHz, respectively, while maintaining the retention time of 25 μs. The 4T bit-cell with the logic design rule only occupies 0.12 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, which is 1.5× lower than the two-port 8T SRAM cells in the PDK, while 1.1× larger than the single-port 6T SRAM.