A 70 pW Self-Compensated Subthreshold Voltage Reference Achieving 190 °C Temperature Range and 0.07%/V Line Sensitivity

This work presents a picowatt self-biased and self-compensated CMOS voltage reference for high-accuracy and ultra-low-power applications. By self-compensating the reverse-biased diode leakage (RBDL) in the core transistors which work in the subthreshold regions, the proposed design simultaneously achieves extremely low power consumption and wide operating-temperature range, without degrading the output accuracy. Fabricated in a 0.18-μm CMOS technology, the circuit occupies an area of 0.009 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The measured results indicate that the designed circuit can generate an average voltage reference of 330 mV with a standard deviation of 2.6 mV at room temperature. With the proposed self-compensation scheme, the average temperature coefficient of 10 dies is 94 ppm/°C over a wide temperature range of 190 °C (from −40 °C to 150 °C). Moreover, it consumes only 70 pW at room temperature and achieves a line sensitivity of 0.07%/V.