Low Offset, High-Resolution Threshold Logic Design in 22nm FDSOI

This paper provides a case study for enhancing Threshold Logic (TL) performance by exploiting the back-gate bias control offered by 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology across three process corners and five temperatures under transient noise. The paper demonstrates how back-gate biasing changes the threshold voltage and reduces the offset from 500µV to 400µV. Moreover, the improvement of 200µV in symmetric offset range and 100µV in input resolution are observed in comparison to conventional biasing. These improvements come at the cost of increased energy dissipation at temperatures higher than 27°C. The accuracy detection is slightly better under conventional biasing with an improvement of 30µV differential input range at 125°C. The back gate biasing results in a marginal shift of the graph by 0.03% at −55°C to a maximum of 8% at 125°C in comparison to the conventional biasing.