A Capacitor-Saver Redundant SAR ADC to Optimize Readout in Compute In-Memory Systems

This paper presents an analysis of the application of an intentionally mismatched capacitive Digital-to-Analog Converter (CDAC) to improve the area efficiency and accuracy of successive-approximation register (SAR) analog-to-digital converters. The proposed SAR ADC architecture, the redundant capacitor-saver SAR ADC, utilizes 1-bit redundancy with intentional mismatch to estimate an additional resolution bit. This redundancy bit not only enhances noise tolerance but also achieves higher resolution through area- and energy-efficient computations, without requiring the addition of non-ideal, area-consuming, and energy-intensive capacitors to the CDAC block of the conventional SAR ADC. Simulations were conducted using Cadence TSMC 130nm CMOS technology and MATLAB software for conventional, redundant, and redundant capacitor-saver SAR ADCs, demonstrating 3 dB and 2 dB improvements in SNDR and SFDR, respectively, when using the capacitor-saver DAC architecture.