A Digital Jitter Correction Technique For High-Speed ADC-Based Communication Links

This paper presents a system-level solution to correct the jitter noise originating from the phase-locked loop (PLL) in transceiver systems. The solution circumvents the traditional power-noise trade-off present when optimizing the phase noise within a PLL, which quickly dominates the system power for high-speed communication. It reduces the power scaling from a fourth-order dependence on system precision down to a second-order scaling. A digital jitter correction method is proposed that uses a reference sinusoid provided by the transmitter to measure and correct jitter errors, allowing the reference itself to be noisy. Only a limited overhead in system bandwidth and dynamic range is required for the reference. A digital signal processor (DSP) performs the post-processing on the received data and can be inserted into existing analog-to-digital converter (ADC) based communication systems. The proposed jitter correction method is experimentally validated by means of a prototype PCB with off-the-shelf components using a 39-MS/s ADC with 75.5 ps<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</inf> of jitter on its clock. An improvement of 10.5 dB in the signal-to-noise ratio (SNR) in the jitter-dominated region is observed, at the cost of only a 15% reduction of the system bandwidth and 1/9th of the input swing of the receiver PCB.