Using Greedy-Enhanced Heuristic to Optimize Instruction Scheduling for RISC-V DSP

With the rapid growth of the Internet of Things (IoT) and embedded systems, the demand for RISC-V architecture in DSPs (Digital Signal Processors) has increased significantly, making processor performance optimization a key research focus. As a core aspect of compiler optimization, instruction scheduling significantly affects execution efficiency and system performance. However, existing heuristic scheduling methods often fail to fully exploit hardware features. To address these limitations, this paper proposes a greedy-enhanced heuristic scheduling strategy that integrates the greedy algorithm’s fast decision-making with an adaptive weighted scoring model to prevent local optima. This approach effectively balances multiple factors such as instruction latency, register pressure, and resource conflicts, thereby enhancing scheduling performance. Experimental results on the RISC-V DSP platform, SummerCore, show that the proposed method achieves significant performance gains, with an average improvement of over 5% compared to LLVM -O3 optimization across multiple benchmarks.