Design Automation and Optimization of Reflective Type Lumped Element Phase Shifters

This paper discusses the design automation and optimization of a digitally tunable reflective type lumped element phase shifter. The phase shifter is based on a branch-line coupler built using capacitors and inductors. The reflective load to this coupler is provided using a digitally tunable capacitor bank. To test the automation algorithm, a 5-bit 180° reflective type phase shifter (RTPS) at 3 GHz was designed using TSMC 65nm CMOS technology. The RMS phase error of this RTPS is less than 3°over a bandwidth of 240 MHz (2.76 GHz - 3 GHz), with a minimum value of 0.3° at 3 GHz. The insertion loss is about 7.3 3 dB. The runtime of the optimization code is about 120-150±seconds on an i9 system with 32 GB memory.