A 10Gb/s PI-Based Quarter Rate all Digital CDR with Improved Linearity

This paper presents a novel quarter-rate Clock Data Recovery (CDR) topology, wherein the phase-tracking loop is implemented using eight Phase Interpolators (PIs). Each PI provides 15 discrete steps between every 45° phase increment, enabling the accurate detection of edge or data samples during plesiochronous operation. The PI is digitally controlled by a circuit topology that facilitates both coarse and fine phase adjustments, thereby enhancing linearity and minimizing Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) errors.Phase selection within the CDR is governed by a digital majority vote scheme and a four-bit digital counter. The design and layout were executed using 65nm CMOS technology, targeting a data rate of 10Gb/s and an operating frequency of 2.5GHz for the PI. This setup achieves an angular resolution of approximately 2.81° per code, with a standard delay of 3.125ps. The proposed system was validated through simultaneous post-layout simulations, incorporating the PI, CML2CMOS buffers, and CML latches. Additionally, Verilog-AMS simulations were used to model jitter generation within a pseudo-random bit sequence (PRBS) and to design the corresponding digital logic operations.