A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit

In the conventional RRAM design, differential reading for odd and even bitlines (BLs) facilitates high-speed data retrieval, but this comes at the cost of area overhead due to additional multiplexers, and is prone to causing performance degradation with inaccurate timing signals. In this work, a high performance RRAM macro is presented to solve the above problems through: 1) a compact dual-wordline (WL) array structure that splits the WLs into odd and even pairs, the inactive half of the BLs can be used as differential input without the extra multiplexers, thereby improving the storage density and reducing WL switching power consumption by 45%; 2) a replica BL control circuit to effectively track the BL discharge characteristics and accurately control WL pulse width, thus lowering read energy consumption and latency. A 1Mb RRAM macro with 64-bit bandwidth and 8.85Mb/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> storage density is implemented using 28nm process, achieving a 3.5ns read cycle and consuming 9fJ per bit during reads, with the FoM (read throughput / area) at least 3.6× higher than prior works.