An Expandable Digital Delay Line using Phase Interpolator with Duty Cycle Correction Capability

This paper describes an expandable digital delay line to achieve both a wide delay range and fine delay resolution. The proposed delay line has coarse and fine delay lines with almost identical unit delay cells. The coarse delay line has a classical configuration of cascaded connection for easy expansion of the delay range. The fine delay line applies phase interpolation to the signals before and after the unit delay cell for fine delay resolution. This architecture allows easy expansion of the delay range while keeping the fine resolution. The delay line also has duty cycle corrector for the clock signal using the simple structure of additional PMOS and NMOS onto the phase-mixing node. Measurement results of the test-chip show the basic concept of the proposed delay line was effective. This delay line has a well-balanced performance and achieves the finest resolution (almost half) of any published delay lines with a delay range of 1 ns or greater.