A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs

This paper presents a high-speed, low-noise and low-offset dynamic latch comparator. In this work, a pair of auxiliary reset transistors is employed to increase the gain of the preamplifier while reducing the reset delay of the latch, which effectively improves the precision and speed of the comparator. The proposed comparator is controlled by two clocks, and the preamplifier is turned on before the regeneration phase to reduce the input-referred noise. In order to reduce power consumption and kickback noise, the preamplifier achieves dynamic operation by controlling a pair of cascode transistors while separating the regeneration node and the input pair. Otherwise, this work optimizes an efficient background calibration circuit to correct the offset. The proposed comparator has been designed and simulated in 12-nm FinFET CMOS technology. Simulation results show a delay of 20 ps at 10 mV input. The proposed comparator also achieves a 0.61 mV input-referred noise and an offset standard deviation of 1.9 mV.