Network-on-Interposer Co-Design for Heterogeneous Chiplet-Based Integrated Systems

A co-design methodology is proposed for heterogeneous integrated systems with active interposers. Bus-based topologies are impractical for heterogeneous systems due to the latency of the chiplet interfaces which degrades the data transfer process. System-on-chip and Internet-of-Things applications present very different tradeoffs for interposers than compute-based systems. A network-on-interposer methodology is proposed which balances cost and system performance. Active interposers are shown to exhibit less than half the latency of passive interposers when interfacing between 7 nm and 45 nm chiplets. Design considerations for both passive and active interposer-based systems are explored in this paper, such as maximum bandwidth, chiplet placement, voltage conversion, and network area.