The Algorithmic and Architectural Optimizations for Highly Efficient Tensor Decomposition Engines

This paper presents efficient algorithm and architectures for tensor decomposition based on field programmable gate array (FPGA). Based on the parallel HOOI (PHOOI) algorithm, a circuit structure is presented to reduce the complexity and to improve the efficiency of tensor decomposition engine. Furthermore, a novel algorithm and architecture are proposed to reduce the number of iterations and enhance the throughput. The proposed circuit achieves parallel processing with a minimum increment of hardware complexity. Both proposed architectures are designed and implemented on the FPGA platform. Evaluation results show that the efficiency of proposed architectures is enhanced by 40% and 60% respectively.