A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI

This paper presents the design of a 128 GS/s 64x time-interleaved SAR ADC, featuring an ultra-wideband two-rank hierarchical track-and-hold architecture maintaining 62 GHz bandwidth in 22nm CMOS FD-SOI technology. To achieve both, high bandwidth and concurrently adequate sampling linearity, an inductively peaked input network and first-stage source follower with pseudo-differential gain coupling is used, taking advantage of a dual -0.5V and 0.9V power supply. The front-end T/H also utilizes a mix of static and dynamic body-biasing techniques enabled by the 22nm CMOS SOI technology to further improve the linearity and signal gain. Each second-level buffer drives four 6-bit asynchronous loop-unrolled SAR ADCs at a conversion rate of 2 GS/s, using speed-optimized dynamic logic cells and MDAC redundancy to fulfil the sampling speed requirements. Time-interleaving mismatch effects such as gain, offset and sample skew errors are calibrated off-chip. The total signal bandwidth across the input network, first-level buffer and T/H stage exceeds 62.2/53.9 GHz and the ADC achieves a SNDR of well above 35.5/32.3 dB up to 19.7 GHz as well as 31.7/28.6 dB up to Nyquist-frequency in TT/SS corner.