A 40V High-Speed Low-FoM Capacitive Level Shifter with Feedback Discharge Control for Floating Supply Gate Drivers on BCD Technology

A high-speed low-figure-of-merit capacitive-coupled level shifter tailored for high-side bootstrapped gate drivers is presented. Key techniques include a Feedback Discharge Control (FBDC) for improved dV/dt Immunity, a MisMatch Reduction Circuit (MMRC) in combination with Common-Mode Blanking Pulse (CMBP) to block common-mode signals with improved mismatch tolerance. The level shifter is fabricated in a 0.75µm STMicroelectronics BCD process and covers a chip area of 0.048mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Experimental results demonstrate a Propagation delay (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>) of 1.525ns and Transition Energy (E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>) of 29.77pJ at 40V, with a dV/dt immunity of up to 20V/ns. The level shifter achieves a figure-of-merit 2 (FoM2) of 2.68ns.pJ/um<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>.V, an improvement of 2x from the recent literature, and exhibits a mismatch tolerance of 20%. The design has been tested at a switching frequency (F<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</inf>) of up to 55MHz. The design is validated through standalone and integrated testing in a DC-DC buck converter.