Zero-shot Learning in Performance Prediction of Digital VLSI Circuits

The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> times, all the while maintaining superior accuracy compared to traditional simulators.