A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor

This paper presents an adaptive clock generator designed in all-digital fully-synthesizable manner for fast frequency management in AI processor. To adapt frequency for dynamic AI workloads, a multi-phase clock chain is designed and a phase picker dynamically switches clock phases to stretch or shrink clock frequency. The digital loop control of PLL employs a coarse exponential and fine phase frequency locking to improve locking time. To ensure the stability, a well-organized floorplan is targeted during the EDA backend flow. Our adaptive clock generator is implemented on 22nm with an AI processor design. The evaluation results demonstrate the design achieves fast clock frequency adjustment within a delay of 1 clock cycle, with advanced area, power, and response time metrics.

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Publication Details

Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043895
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
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article

A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor

Le Ye, Xueping Liu, Tianyu Jia
Advancements in PLL and VCO Technologies
article

A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor

Le Ye, Xueping Liu, Tianyu Jia
article en

Abstract

This paper presents an adaptive clock generator designed in all-digital fully-synthesizable manner for fast frequency management in AI processor. To adapt frequency for dynamic AI workloads, a multi-phase clock chain is designed and a phase picker dynamically switches clock phases to stretch or shrink clock frequency. The digital loop control of PLL employs a coarse exponential and fine phase frequency locking to improve locking time. To ensure the stability, a well-organized floorplan is targeted during the EDA backend flow. Our adaptive clock generator is implemented on 22nm with an AI processor design. The evaluation results demonstrate the design achieves fast clock frequency adjustment within a delay of 1 clock cycle, with advanced area, power, and response time metrics.

Peking University (CN)
Affordable and clean energy
Openalex Percentile: Top 87%
Advancements in PLL and VCO Technologies
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