A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor
This paper presents an adaptive clock generator designed in all-digital fully-synthesizable manner for fast frequency management in AI processor. To adapt frequency for dynamic AI workloads, a multi-phase clock chain is designed and a phase picker dynamically switches clock phases to stretch or shrink clock frequency. The digital loop control of PLL employs a coarse exponential and fine phase frequency locking to improve locking time. To ensure the stability, a well-organized floorplan is targeted during the EDA backend flow. Our adaptive clock generator is implemented on 22nm with an AI processor design. The evaluation results demonstrate the design achieves fast clock frequency adjustment within a delay of 1 clock cycle, with advanced area, power, and response time metrics.
Authors
- Le Ye (ORCID: https://orcid.org/0000-0003-0599-7762)
- Xueping Liu
- Tianyu Jia (ORCID: https://orcid.org/0000-0002-4570-4613)
Institutions
- Peking University (CN)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11043895
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00