A 172.1dB-FoM 19.5kHz-BW DT ΔΣ ADC Using CLS-Assisted Fast Self-Quenching Floating Inverter Amplifier with Sampling Noise Cancellation

This paper presents a power-efficient discrete-time (DT) delta-sigma analog-to-digital converters (ΔΣ ADC) using a correlated level shifting (CLS)-assisted fast self-quenching floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS technique improves the equivalent open-loop gain of the FIA, while the SNC technique minimizes the sampling noise of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage integrator. Compared with the conventional FIAs, the fast self-quenching FIA reduces power consumption while ensuring adequate gain. The prototype of the 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-order DT ΔΣ ADC with the proposed FIA is fabricated in a 65-nm CMOS process and achieves fully dynamic operation. It realizes an 88.0dB peak signal-to-noise-and-distortion ratio (SNDR) with an oversampling ratio of 256 for a 19.5kHz bandwidth while consuming 76.2µW from a 1.2V supply at a 10MHz sampling frequency. This ΔΣ ADC achieves 89.6dB dynamic range and 172.1dB SNDR-based Schreier figures of merit.