An Efficient Hardware Implementation of 2D Convolution based on the Discrete Hirschman Transform

A highly efficient 2D convolutional algorithm based on the Discrete Hirschman Transform (DHT), known as DHT-Conv, has recently been developed. This method demonstrates superior performance compared to FFT-based convolution (FFT-Conv) in terms of computational complexity. In this paper, we implement DHTConv on Field Programmable Gate Arrays (FPGA) and evaluate its hardware performance on both Altera and Xilinx FPGA devices. The results from the Altera device indicate that our DHTConv significantly outperforms FFT-based convolution, yielding over 22% savings in real computations and approximately 5% in latency. Additionally, the results from the Xilinx FPGA board show that DHTConv requires fewer hardware resources compared to FFTConv, achieving over 16% savings in LUTs, 48% savings in flip-flops, and 61% savings in DSP blocks.