Robust Defect Detection for Phase-Locked Loops using All-Digital Built-In Self-Test (BIST) Circuitry

The rising demand for defect-free integrated circuits (ICs), especially in the mission-critical automotive industry, has stimulated the development of more efficient defect detection methods. Currently, defect testing methods for digital circuits are far more advanced than for analog circuits, largely due to the greater functional complexity of analog designs. However, in the automotive industry, almost 80% of IC failures stem from defects in analog circuits, creating an urgent need for robust and cost-effective defect detection techniques for analog and mixed-signal (AMS) circuits. This paper presents an all-digital defect detection approach for charge-pump phase-locked loops (CP-PLLs). The proposed Design for Test (DFT) strategy harnesses the robustness of digital control and monitoring circuits to improve detection accuracy, minimizing false failures. Through extensive transistor-level simulations, we demonstrate that the proposed method achieves a high defect coverage of over 97.5% with minimal chip area (< 0.1%) requirements for the BIST circuits.