A 10-bit SAR ADC With a Low-Kickback-Noise Comparator and a Process-Variation-Independent Capacitive DAC for Biosensing Applications

A successive approximation register analog-to-digital converter (SAR ADC) featuring a novel low-kickbacknoise comparator is proposed in this work. In addition, a systematic capacitor-array layout method, which effectively resists first-order process variations, is proposed. The proposed chip uses a 0.35 μm 2P4M CMOS process and occupies only 0.17mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. With a 3.3-V power supply and a 125-kS/s sampling rate, it consumes only 29.3 μW and achieves a 9.3-bit effective number of bits, resulting in 34.1-fs/Ω•step normalized figure-of-merit. The measured maximum integral nonlinearity and differential nonlinearity are 0.49 LSB and 0.54 LSB, respectively.