ASF-CRB: an Energy-Efficient Activity-Balanced Charge-Recycling Bus Architecture Based on Alternate Signal Flipping

Charge-recycling bus (CRB) achieves quadratic energy savings by stacking two data channels between VDD and VSS. However, it suffers from middle voltage (VMID) drift due to unbalanced data activities of the two channels, which increases signal propagation delay and causes timing violations. In this paper, we present ASF-CRB, a CRB architecture that addresses the VMID drift problem at minimum energy costs based on a novel data transmission scheme named Alternate Signal Flipping (ASF). By reconfiguring the signal transmission path every cycle through a multiplexer at each pipeline stage, ASF ensures all bits flip once in every two pipeline stages. This averages each channel's high and low activities to 50% and thus contributes to balanced data activities between stacked channels. Lightweight latch structures tailored to CRBs are presented to minimize the delay and energy overheads, and a complete ASF-CRB architecture is developed for applicability in VLSI systems. The proposed ASF-CRB is implemented at a 28nm CMOS process. Post-layout simulations show that ASF-CRB achieves up to 41.0% energy saving at similar VMID stability and ∼2.7× smaller VMID drifts at similar energy consumption compared with the state-of-the-art CRB structure.