Design Analysis of Memristor-Based 7T SRAM Using Heterojunction Tunneling Transistors

Power consumption is considered one of the most important issues in memory scaling technology. Static random-access memories (SRAMs) contribute significantly to the dissipation of dynamic and static power in various processors used to manufacture portable devices, buffers, caches, reservation stations and so on. Technology scaling also maximizes the leakage current to a greater extent and reduces the efficiency of memory circuits. Therefore, it is essential to introduce nonvolatility and low-power consumed transistors in memory circuits to enhance memory performance and reduce both leakage current and power consumption in circuits. In this conflict, memristors can strengthen their roots in the VLSI domain compared to other emerging devices. Also, heterojunction tunneling transistors (HETTs) are widely utilized to minimize power consumption in ultralow power applications. Therefore, this research aims to develop a two-memristor-based 7T SRAM (2M-7T SRAM) using HETT technology to minimize the leakage of power and current in memory circuits. Moreover, the proposed memory cell performs both read and write functions to show the read/write constancy of the proposed memory cell. Compared to the existing 7T SRAM, the proposed 2M-7T SRAM achieves 0.569[Formula: see text] [Formula: see text] leakage current at 1[Formula: see text]V supply voltage, which is noticeably fewer than the state-of-the-art memory designs. Also, it consumes 0.010[Formula: see text] [Formula: see text] and 0.060[Formula: see text] [Formula: see text] read and write power, which is lower than the existing SRAM designs.