Multi-Domain IVRs for Chiplet-Based Processors: Towards Energy-Efficient Power Delivery

The use of advanced processors in the contemporary world results in the implementation of the chiplet architectural design for better scalability, higher performance, and relatively affordable prices. However, power delivery is still problematic in such architectures because interconnects consume more power, the power distribution is nonuniform and this architecture has high power density. Coping with these challenges, the present paper aims to describe the design and implementation of the multi-domain integrated voltage regulators (IVRs) concerning chiplet-based processors with an emphasis on the aspects of energy-saving power delivery. Introducing a new multi-domain IVR which regulates the voltage across chiplets both for getting the better performance of the system and for reducing its power consumption. In order to optimize conversion efficiency and maintain thermal stability, our design adopts DVS, load awareness and adaptive feedback mechanisms. Other than that the conventional mono-voltage regulators, our methods provide discrete control of voltage over many domains leading to lower power wastage in the system. To confirm the effectiveness of our strategy, we perform realistic and experimental results using standard processor benchmarks. The outcomes show that the adopted IVR architecture can increase the power conversion efficiency by up to 20% and decrease thermal hotspots by 15% as compared to traditional power delivery methods. Furthermore, the proposed adaptive power management approaches results in turning off voltage droops and improvements in load voltage balancing, so that the total computational throughout increases by 10%. From these results, it is clear that the application of multi-domain IVRs open to opportunities in managing power in chiplet-based processors for the development of subsequent generation energy-dependent computing systems