An Energy-Efficient IF Spiking Neuron with Enhanced Spike Encoding Capability

The significance of developing more efficient spiking neurons is increasing due to advances in neuromorphic chips and Spiking Neural Network (SNN) models. In this paper, an energy-efficient and miniaturized spiking neuron is proposed with improved noise susceptibility and encoding efficiency. The key idea behind developing this circuit is to modify the conventional integrate-and-fire (IF) mechanism and control the resetting time of the spike voltage while maintaining its compactness and minimal energy consumption. This facilitates adjustable spike width and frequency, improving data post-processing efficiency. Moreover, the area and energy per spike are achieved at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.702 \mu m^{2}$</tex> and 0.663 fJ, respectively. Additionally, employing an adequate supply voltage ensures an acceptable signal-to-noise ratio (SNR) for effective noise extraction while balancing energy consumption and driving capability. The Cadence Virtuoso tool is utilized to construct and simulate the circuit, and experimental testing is performed for functional evaluation. Furthermore, the neuron circuit is implemented and evaluated with both single and multiple current sources, and the layout is designed. Hence, the proposed design possesses unique features with parametric enhancements, demonstrating its potential for use in neuromorphic chips.