TinyMLDPD: FPGA Implementation of TinyML Digital Predistortion Leveraging Bipartite Tables

Digital Predistortion (DPD) is essential for enhancing the efficiency of power amplifiers (PAs) in modern wireless communication systems by mitigating nonlinear distortions and memory effects. Neural network-based DPD has emerged as a powerful approach due to its ability to model complex PA behaviors. In this work, we propose TinyMLDPD, a lightweight neural network-based DPD that maintains high accuracy while reducing hardware complexity. Our approach employs a fully connected feedforward neural network inference which utilizes 821 coefficients. In addition, we present a symmetric bipartite table method (SBTM) for efficient activation function computation. Implemented on an AMD Zynq UltraScale+ ZCU106 field-programmable gate array (FPGA) Device, the proposed architecture is flexible enough to support online training with reasonable enhancements, making it a practical solution for realworld deployment.

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Publication Details

Published
2025-04-11
DOI
https://doi.org/10.1109/dcas65331.2025.11045478
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
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article

TinyMLDPD: FPGA Implementation of TinyML Digital Predistortion Leveraging Bipartite Tables

Shahriar Shahabuddin, Nicholas Day, Alex Dhrubo Malakar
Parallel Computing and Optimization Techniques
article

TinyMLDPD: FPGA Implementation of TinyML Digital Predistortion Leveraging Bipartite Tables

Shahriar Shahabuddin, Nicholas Day, Alex Dhrubo Malakar
article en

Abstract

Digital Predistortion (DPD) is essential for enhancing the efficiency of power amplifiers (PAs) in modern wireless communication systems by mitigating nonlinear distortions and memory effects. Neural network-based DPD has emerged as a powerful approach due to its ability to model complex PA behaviors. In this work, we propose TinyMLDPD, a lightweight neural network-based DPD that maintains high accuracy while reducing hardware complexity. Our approach employs a fully connected feedforward neural network inference which utilizes 821 coefficients. In addition, we present a symmetric bipartite table method (SBTM) for efficient activation function computation. Implemented on an AMD Zynq UltraScale+ ZCU106 field-programmable gate array (FPGA) Device, the proposed architecture is flexible enough to support online training with reasonable enhancements, making it a practical solution for realworld deployment.

Oklahoma State University (US)
Openalex Percentile: Top 86%
Parallel Computing and Optimization Techniques
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