Partitioning FPGAs for Optimized Utilization

When one considers execution of tasks in data center, FPGAs (Field Programmable Gate Arrays) based accelerators can offer speed-up in execution for a wide variety of tasks and are more power-efficient. Recently developments are seeing more of the integration and use of these accelerators in datacenters. The efficient utilization of FPGAs within this context in cloud data centers is still an open research problem. In this work, we explore FPGAs characteristics and resources and discuss efficient means to implement accelerators using these resources. Specifically, we discuss a partitioning model that minimizes the number of idle resources in an FPGA field during partitioning. The proposed partitioning approach is modeled as an exact optimization problem; the model was validated using the CPLEX Optimization Tool. We report on initial results obtained and discuss possible future work.