An Efficient VLSI Design Of Pipelined Advanced Encryption Standard For Cryptography

This article presents a VLSI design of a pipe-led 128-bit Advanced Encryption Standard (AES) adapted to image cryptography, focusing on the use of effective area in FPGA implementation. The design improves subbits and MixColumns transformation, which greatly contributes to the consumption of AES machine -machine resources. By evaluating the balance between clock cycles and efficiency in the area, a customized date is developed to increase performance by reducing resource use. A new 32-bit Datapath architecture has been introduced to facilitate parallel encryption of 128-bit data blocks with low hardware complexity. The implementation benefits from the shift register in shifts, MixColumns and larger expansion stages, significantly reduces consumption of the area, which ensures high throws. The proposed AES architecture is developed in Verilog HDL and tested using models 6.4C and Matlab, and achieves a throw of 692.65 MB/s with a street number of only 5.65K when it is synthesized using the Xilinx tool.