Performance of Gate Stack Silicon on Insulator and Gate Stack Pocket‐Doped Silicon on Insulator Tunnel FETs with Interface Trap Charges

In this article, the effect of interface trap charges (ITCs) on Gate Stack Silicon on Insulator (GSSOI) and GSSOI with counter‐doped pocket (GSCDPSOI) tunnel field effect transistors (TFETs) has been highlighted using Sentaurus TCAD simulator. Such analysis is reported for two different trap distributions like Gaussian and uniform trap distributions. The various parameters like electron density, transfer characteristics, electric field, energy band diagram, subthreshold swing, and current ratio are reported for these TFETs under the presence of Gaussian and uniform distribution of trap charges. Further, the RF/analog performance like transconductance ( g m ) and cut‐off frequency ( f T ) are extracted for these TFETs considering Gaussian and uniform distribution of trap charges. It is seen that the electrical parameters of GSCDPSOI TFET are more immune to ITCs compared to GSSOI TFET. Moreover, the presence of pocket in GSCDPSOI TFET leads to enhanced BTBT rate; thus, the performance of electrical behavior is improved.